1. Field of the Invention
The present invention relates to a DC/DC converter, and in particular to a DC/DC converter using fixed ON time control.
2. Description of Related Art
DC/DC converters are widely adopted for use in power sources for liquid crystal televisions, digital versatile disc (DVD) players, Blu-ray Disc players, plasma display panels (PDPs), and the like.
Patent document 1 (Unexamined Japanese Patent Application Publication No. 2008-29159) provides a DC/DC converter performing fixed ON time pulse frequency modulation (PFM) control, that has a simple control circuit configuration, lowers switching frequency under light loads to reduce power consumption, and operates at an approximately constant switching frequency under heavy loads regardless of variations in input/output voltage. For this purpose, the converter is provided with a control circuit that performs pulse frequency modulation control such that the switching element has a fixed ON time and a variable OFF time. The control circuit links the ON time of the switching element to variations in at least one of an input voltage and an output voltage. Specifically, the ON time of the switching element, i.e., a switching transistor supplying energy to an inductor, is reduced as input voltage increases, or increased as output voltage increases.
The control circuit described in Patent document 1 has an error amplifier for amplifying the error between the output voltage and a target voltage, an oscillator whose frequency increases or decreases based on an error signal output by the error amplifier, and a one-shot circuit that is triggered by a frequency signal output by the oscillator, generating a specific ON time. The one-shot circuit includes a capacitor, a current supply circuit that supplies charging current to the capacitor, and a voltage detecting circuit that detects whether the voltage of the capacitor has surpassed a preset voltage.
Patent document 2 (Unexamined Japanese Patent Application Publication No. 2009-148155) proposes an internal ripple generating, fixed ON time voltage regulator with increased output voltage accuracy for a DC/DC converter using fixed ON time control.
According to paragraph 3 of Patent document 2, an output capacitor with an arbitrary equivalent series resistance (ESR) value is provided for the purpose of improving output voltage accuracy. According to paragraph 0009, the voltage regulator using fixed ON time, i.e., constant ON time, control is a type of voltage regulator that uses ripple mode control. According to paragraph 0011, it is possible to minimize noise and reduce variation in load voltage by reducing the ripple, but this impedes ripple mode voltage regulation. Reducing ripple size also decreases the comparison voltage differential, greatly impeding swift and accurate comparison. U.S. Pat. Nos. 7,482,791 and 7,482,793 may be referred to as patents of the same family as patent document 2.
U.S. Pat. Nos. 7,443,148, 7,482,791, and 7482793 may be referred to as patents of the same family as patent document 3 (Unexamined Japanese Patent Application Publication No. 2009-148157). Patent document 3 relates to patent document 2, and proposes a constant ON time voltage regulator with an increased maximum duty cycle. Provided within is a DC/DC converter with a fixed (constant) ON time, minimum OFF time control loop. Patent document 3 includes a fixed ON time control circuit that receives an input voltage, provides a switching output voltage on a switch output node using a minimum ON time, variable OFF time feedback control loop, and generates a first signal for turning off a high-side switch at the expiration of a first ON time duration or at the expiration of a maximum ON time. The first ON time duration is at least a minimum ON time and is allowed to expand to a maximum ON time when the feedback voltage remains less than a reference voltage.
Patent document 4 (U.S. Pat. No. 7,714,547) discloses a fixed ON time switch mode DC/DC converter. In FIG. 1 therein, a fixed ON time DC/DC converter 10, a regulation circuit 12, a combining circuit 16, and a slope signal generator 18 are provided. The regulation circuit 12 is provided with a comparator 14, a one-shot timing circuit 30, and an S-R flip flop 32.
Patent document 5 (Unexamined Japanese Patent Application Publication No. 2010-226930) provides a DC/DC converter enabling stabilization of switching frequency. According to paragraph 0003 thereof, a fixed ON time DC/DC converter using a comparator compares an output voltage to a reference voltage, and controls (for instance, turns ON) a switch (transistor) for a constant period using a signal generated in accordance with the results of the comparison. Thus, output voltage is regulated by regulating the OFF period of the switch.
According to paragraph 0005 of patent document 5, when the input voltage, output voltage, or output current of the DC/DC converter using a comparator varies, the switching duty ratio of the switch varies. This causes switching frequency (switching period) to vary. Such variation in switching frequency forebodes difficulties in preventing noise generated by switching. This is because, when frequency is constant, it is possible to take noise prevention steps suitable for that frequency. Patent document 5 also points out that when a plurality of DC/DC converters are operated, a problem arises in that electromagnetic interference (EMI) noise is generated by the mutual interference among the plurality of switching frequencies arising from the differences in switching frequency between the DC/DC converters.
FIG. 3 illustrates a synchronous rectifier buck DC/DC converter using fixed ON time control subjected to an experiment conducted during the process of arriving at the present invention. Much of the circuitry of a DC/DC converter 30 is contained within an integrated circuit IC3. The integrated circuit IC3 has a high-side transistor QH and a low-side transistor QL. The low-side transistor QL functions as a synchronous rectifier transistor. A first primary electrode D of the high-side transistor QH is connected to an input voltage VIN, and a second primary electrode S thereof is connected to a first primary electrode D of the low-side transistor QL.
The high-side transistor QH and the low-side transistor QL may both be configured as, for example, n-channel MOS transistors, but are not limited thereto. For instance, a combination of an n-channel and a p-channel MOS transistor is also acceptable. Rather than a MOS transistor, a bipolar transistor configuration is also acceptable.
A second primary electrode S of the low-side transistor QL is connected to a ground potential GND.
Drive signals SDH and SDL are input to control electrodes G of the high-side transistor QH and the low-side transistor QL, respectively. The drive signals SDH and SDL are synchronous with each other, and the polarities thereof are set so that the ON/OFF states of the high-side transistor QH and the low-side transistor QL are the inverse of each other.
This document uses the terms “first primary electrode”, “second primary electrode”, and “control electrode” to refer to the various transistor electrodes. In the case of a MOS transistor, a first primary electrode may at times be a drain electrode or a source electrode. Because a second primary electrode may likewise be at times a source electrode or a drain electrode, it is impossible to define the electrodes as one specific type. However, a control electrode may be defined as a gate electrode. The same applies in the case of a bipolar transistor. What is referred to as a first primary electrode may be at times a collector electrode or an emitter electrode, and what is referred to as a second primary electrode may be at times an emitter electrode or a collector electrode, making it impossible to define the electrode as either type. However, a control electrode may be defined as a base electrode.
The second primary electrode S of the high-side transistor QH and the first primary electrode D of the low-side transistor QL have a common connection, and the common connection point thereof is connected to an external terminal T1. The external terminal T1 is one of the external terminals provided on the integrated circuit IC3, and in particular the external terminal T1 is equivalent to the output terminal of the DC/DC converter 30. The integrated circuit IC3 has numerous terminals apart from the external terminal T1, but these have been omitted from the drawing for simplicity of description.
An inductor L1 and an output capacitor C1 are connected in series between the external terminal (output terminal) T1 and the ground potential GND. An output voltage VOUT is output from the common connection point of the inductor L1 and the output capacitor C1.
The input voltage VIN supplied to the first primary electrode D of the high-side transistor QH is stepped down to a lower voltage, and the output voltage VOUT is output from the second primary electrode S of the high-side transistor QH. The magnitudes of the input voltage VIN and the output voltage VOUT are, for example, 12V and 5V direct current voltages, respectively.
FIG. 3 depicts a synchronous rectifier buck DC/DC converter that also constitutes a fixed ON time control DC/DC converter. The fixed ON time control DC/DC converter 30 has a one-shot circuit 30A.
The one-shot circuit 30A outputs a one-shot pulse PS1 to an output terminal of a comparator CMP1. The one-shot pulse PS1 is inputted to, for example, an S-R flip flop not shown in the drawings.
The one-shot circuit 30A has a current mirror circuit CM1. The current mirror circuit CM1 has at least one pair of transistors with an MOS or bipolar configuration. A constant current I1 is output from one terminal of the current mirror circuit CM1, and the constant current I1 travels from a first primary electrode D of a transistor Q1 to a second primary electrode S.
An inverting input terminal (−) of an operational amplifier OP1 and the second primary electrode S of the transistor Q1 have a common connection, and a resistor R1 is connected to the common connection point thereof. For this reason, the constant current I1 is determined by the voltage of the inverting input terminal (−) of the operational amplifier OP1 and by the resistor R1. Due to the circuit operation of the operational amplifier OP1, the voltage of the inverting input terminal (−) of the operational amplifier OP1 is equal to a reference voltage VB1 input to a non-inverting input terminal (+) of the operational amplifier OP1. The reference voltage VB1 is determined by the magnitudes of an input voltage VIN and resistors R2 and R3. The constant current I1 is accordingly expressed by numerical formula 1, where r1 is the resistance value of the resistor R1.
                              (                      Numerical            ⁢                                                                      ⁢                                                                    ⁢            Formula            ⁢                                                  ⁢            1                    )                ⁢                                                                                                I          ⁢                                          ⁢          1                =                              VB            ⁢                                                  ⁢            1                                r            ⁢                                                  ⁢            1                                              (        1        )            
The constant current I1 generated by the operational amplifier OP1, transistor Q1, resistors R1 through R3, and input voltage VIN is output from the other terminal of the current mirror circuit CM1, and charges a capacitor C2. The current charging the capacitor C2 can be easily adjusted to be greater or smaller than the constant current I1 depending on the configuration of the current mirror circuit CM1, but, for simplicity of description, is the same within an embodiment of the present invention.
When the capacitor C2 is charged by the constant current I1, and a transistor Q2 is switched ON and OFF at a specified interval, a ramp wave signal ST with superior linearity is generated at one terminal of the capacitor C2, i.e., the non-inverting input terminal (+) of the comparator CMP1. A one-shot pulse PS1 is generated by this ramp wave signal ST.
The amplitude STP of the ramp wave signal ST is determined by a reference voltage VFB3 of the inverting input terminal (−) of the comparator CMP1. The reference voltage VFB3 is determined by an output voltage VOUT and resistors R4 and R5. For instance, when the output voltage VOUT is 5V and the resistance values of the resistors R4 and R5 are 40 KΩ and 10 KΩ, respectively, the reference voltage VFB3 is 1V. Thus, when the ramp wave signal ST reaches 1V, the output of the comparator CMP1 transitions from a low level to a high level, and a one-shot pulse PS1 having an ON period TON1 is output.
The ON period TON1 of the one-shot pulse PS1 is expressed by numerical formula 2, where VIN is inputted voltage, VOUT is output voltage, r1 is the resistance value of the constant current I1 and the resistor R1, and c2 is the capacity of the capacitor C2.
                              (                      Numerical            ⁢                                                  ⁢            Formula            ⁢                                                  ⁢            2                    )                ⁢                                                                                                T                      ON            ⁢                                                  ⁢            1                          =                                            c              ⁢                                                          ⁢                              2                ·                VFB                            ⁢                                                          ⁢              3                                      I              ⁢                                                          ⁢              1                                =                                    VFB              ⁢                                                          ⁢                              3                ·                r                            ⁢                                                          ⁢                              1                ·                c                            ⁢                                                          ⁢              2                        VIN                                              (        2        )            
As is clear from numerical formula 2, the ON period TON1 of the one-shot pulse PS1 output from the one-shot circuit 30A is inversely proportional to the input voltage VIN, and directly proportional to the reference voltage VFB3, i.e., the output voltage VOUT.
Stated otherwise, numerical formula 2 illustrates that when a fixed ON time control DC/DC converter is configured using the one-shot circuit 30A, the ON period TON1 of the switching element is dependent upon the respective magnitudes of the input voltage VIN and the output voltage VOUT.
The inventors discovered that, in a fixed ON time control DC/DC converter using the one-shot circuit 30A, when the load current IL, i.e., the current traveling from the high-side transistor QH toward the inductor L1, increases, the ON resistance of the high-side transistor QH ceases to be negligible, and the ON duty ratio DON of a switching signal SW varies. Specifically, even when the voltage drop in the high-side transistor QH is no longer negligible due to the ON resistance of the high-side transistor QH, because the output voltage VOUT is controlled so as to reach a specific magnitude of, for example, 5V by the circuit configuration of the DC/DC converter, the ON duty ratio DON increases. Stated otherwise, the OFF period TOFF grows shorter, the period decreases, and the operating frequency of the DC/DC converter 30 increases.
When the operating frequency of the DC/DC converter 30 increases, the output voltage VOUT varies due to EMI noise prevention being impeded and the operating point of the ripple generating circuit in the DC/DC converter using a ripple generating circuit varying. The ripple generating circuit will be described below.
FIG. 4 is a schematic illustration of variations arising in the switching signal SW output to the external terminal T1 of FIG. 3. A switching signal SW1 illustrates an instance where the load current IL flowing through the DC/DC converter 30 is comparatively low, i.e., the load is comparatively light; and a switching signal SW2 illustrates an instance where the load current IL is comparatively great, i.e., the load is comparatively heavy.
When the load current IL is comparatively small or the ON resistance RONH of the high-side transistor QH is comparatively low, i.e., when the load is comparatively light, the voltage drop caused by the ON resistance RONH of the high-side transistor QH is negligible, meaning that the amplitude VPSW1 of the switching signal SW1 is roughly equivalent to the input voltage VIN. Here, the switching signal SW1 is illustrated by an ON period TON1, an OFF period TOFF1, and a period T1. The period T1 is expressed as T1=TON1+TOFF1, and the ON duty ratio DON1 of the switching signal SW1 is expressed by DON1=TON1/(TON1+TOFF1).
When the load current IL is comparatively great or the ON resistance RONH of the high-side transistor QH is comparatively great, i.e., when the load is comparatively heavy, the voltage drop caused by the ON resistance RONH of the high-side transistor QH ceases to be negligible, meaning that the amplitude VPSW2 of the switching signal SW2 does not reach the input voltage VIN, but drops by the amount of a voltage drop Vdrop. The voltage drop Vdrop is expressed as the product of the ON resistance RONH of the high-side transistor QH and the load current IL; i.e., Vdrop=RONH×IL. The switching signal SW2 is illustrated with an ON period TON2, an OFF period TOFF2, and a period T2. The period T2 is expressed as T2=TON2±TOFF2, and the ON duty ratio DON2 of the switching signal SW2 is expressed as DON2=TON2/(TON2+TOFF2).
Even when the amplitude VPSW2 of the switching signal SW2 decreases, because the output voltage VOUT is set to a specific amplitude of, for instance, 5V due to the circuit configuration of the DC/DC converter, the OFF period TOFF2 of the high-side transistor QH grows shorter, and the ON duty ratio DON2 grows larger than the ON duty ratio DON1 of the switching signal SW1. That is, the relationship T2<T1 holds between the period T2 of the switching signal SW2 and the period T1 of the switching signal SW1, and the frequency of the switching signal SW2 is greater than that of the switching signal SW1.
Variation in the frequency of the switching signal SW2 hampers prevention of noise caused by the switching of the high-side transistor QH. This is because, while it is possible to provide a band-pass filter that dampens the frequency components when the frequency is constant, such a measure is not possible when the operating frequency of the DC/DC converter 30 varies at random.
FIG. 5 depicts another DC/DC converter 50 provided so as to prevent noise. The DC/DC converter 50, like that of FIG. 3, is a synchronous rectifier buck DC/DC converter using fixed ON time control. The DC/DC converter 50 is characterized in particular in being provided with a ripple generating circuit RI. The DC/DC converter using fixed ON time (constant ON time) control is a ripple mode control type, as suggested by patent document 3.
The DC/DC converter 50 has an integrated circuit IC5. The integrated circuit 105 has at least external terminals T1, T2, T3, and T4. The external terminal T1 is equivalent to the output terminal of the DC/DC converter 50, with an inductor L1 and a output capacitor C1 connected in series between the external terminal T1 from which a switching signal SW is output and a ground potential GND, and an output voltage VOUT is output from the common connection point of the inductor L1 and the output capacitor C1.
The external terminal T1 is disposed at the common connection point of a high-side transistor QH and a low-side transistor QL. The high-side transistor QH is disposed toward an input voltage VIN, and the low-side transistor QL is disposed by a ground potential GND. The high-side transistor QH, low-side transistor QL, inductor L1, output capacitor C1, input voltage VIN, and output voltage VOUT are the same as those illustrated in FIG. 3.
The external terminal T2 is provided so as to lead the inverting input terminal (−) of a comparator CMP2 out of the integrated circuit IC5. A feedback voltage VFB5 consisting of an output voltage VOUT divided by resistors R11 and R12 is returned to the external terminal T2.
The external terminal T3 is provided in order to connect a capacitor C6 that generates a soft start voltage VSS. Such soft start voltage VSS is often used in a DC/DC converter of this kind, and the purpose thereof is to smooth the startup operation of the DC/DC converter 50. A constant current source CC1 and a bandgap voltage circuit BG are connected to the external terminal T3.
The bandgap voltage circuit BG generates a bandgap voltage of, for instance, 1.2V that is not dependent upon the magnitude of a power source voltage VC1 or changes in ambient temperature.
The reference voltage generated by the bandgap voltage circuit BG is used to define the upper limit value of the soft start voltage VSS, or to set the average voltage of the soft start voltage VSS.
In the ripple generating circuit RI, a ripple is superimposed upon the soft start voltage VSS. Properly described, the ripple generating circuit RI functions as a circuit for generating a pseudo-ripple component. The provision of the ripple generating circuit RI can increase the coverage of the output capacitor C1.
Normally, a ripple control DC/DC converter requires an amplitude of a certain size in order to accurately detect output ripple voltage. For this reason, an output capacitor C1 with a comparatively great ESR must be provided. However, it is not preferable for ESR and ripple voltage amplitude to be increased, as this reduces noise resistance properties as well as load voltage properties.
When a ripple generating circuit RI is provided, it can be made to conform to an output capacitor C1 having a desired ESR value. For instance, when the ESR of the output capacitor C1 is high, either no ripple voltage is generated in the ripple generating circuit RI, or the amplitude thereof can be kept low. When the ESR of the output capacitor C1 is low, the amplitude of the ripple voltage generated in the ripple generating circuit RI can be adjusted so as to be high. A specific example of the ripple generating circuit RI will be described below.
A soft start voltage VSS upon which a ripple voltage VRI is imposed is inputted as a reference voltage VREF5 to a non-inverting input terminal (+) of a comparator CM2. An inverting input terminal (−) of the comparator CM2 is connected to the external terminal T2. A feedback voltage VFB5 consisting of an output voltage VOUT divided by resistors R11 and R12 is returned to the external terminal T2.
The comparator CMP2 compares the reference voltage VREF5 upon which the ripple voltage is imposed with the feedback voltage VFB5, and outputs a comparison signal VCMP2. When the feedback voltage VFB5 is greater than the reference voltage VREF5, the comparison signal VCMP2 is of a low level; and, contrariwise, when the feedback voltage VFB5 is less than the reference voltage VREF5, the comparison signal VCMP2 is of a high level.
The comparison signal VCMP2 is inputted to a one-shot circuit OS1 as well as to a set terminal S of an S-R flip flop FF.
The one-shot circuit OS1 outputs a one-shot pulse PS1 using the rising or falling edge of the comparison signal VCMP2. An output voltage VOUT is input to the one-shot circuit OS1 via the external terminal T4. In this way, the one-shot circuit OS1 is retained at a specific circuit operating point by the output voltage VOUT.
The one-shot pulse PS1 output by the one-shot circuit OS1 is inputted to a reset terminal R of the S-R flip flop.
The S-R flip flop FF is set by the comparison signal VCMP2, and outputs an output signal, reset by the one-shot pulse PS1, that is inputted to a driver DRV.
The driver DRV generates drive signals DRVH and DRVL for driving the high-side transistor QH and the low-side transistor QL, respectively. When the high-side transistor QH is in an ON state, the driver DRV generates a drive signal so that the low-side transistor QL switches to an OFF state. The drive signals DRVH and DRVL are not necessarily set at inverse polarities; when the high-side transistor QH and the low-side transistor QL are of different conducting types, drive signals of the same polarity are input synchronously.
The high-side transistor QH is connected to an input voltage VIN, and supplies energy to the inductor L1 connected to the external terminal T1. The low-side transistor QL is provided in order to synchronously rectify the energy accumulated within the inductor L1.
The inventors also discovered that, because an external terminal T2 for inputting the feedback voltage VFB5 to the comparator CMP2 must be provided in the integrated circuit IC5, the number of external terminals on the ripple control DC/DC converter 50 of FIG. 5 increases, and, because these terminals lead outside the integrated circuit IC5, noise resistance properties are reduced.
FIG. 6 illustrates a ripple generating circuit used in the ripple control DC/DC converter of FIG. 5. A ripple generating circuit RI is generated using the switching signal SW output from the external terminal T1. The ripple generating circuit RI is constituted by an operational amplifier OP2, resistors R9 and R10, and a capacitor C3. A reference voltage VR1 is inputted to the non-inverting input terminal (+) of the operational amplifier OP2. A common connection point of the resistor R9 and the resistor R10, and an end of the capacitor C3, are connected to the inverting input terminal (−) of the operational amplifier OP2. The resistor R10 and the capacitor C3 are connected in a row, and constitute a so-called integrating circuit. The switching signal SW is integrated by this integrating circuit and further amplified, and a ramp wave-shaped pseudo-ripple voltage DVR1 is generated at the output of the operational amplifier OP2.